Conventional MOS transistors are fabricated with spaced apart source and drain regions of semiconductor material of one polarity diffused or otherwise embedded in a semiconductor substrate of opposite polarity. An insulating layer is formed over the surface. A first metal layer strip penetrates through a window to the source region and provides the source lead while a second metal strip penetrates to the drain region and provides the drain lead. A third conductive strip lies on top of the insulating layer and overlaps the source and drain regions to provide a gate. Voltage signals at the gate control the flow of current between the source and drain by the effect of the signal field in establishing or enhancing a temporary conductive channel between the source and drain or by blocking or depleting a preformed channel.
A back contact region may also be provided adjacent to and in electrical contact with the source region. The back contact region is of second polarity, that is, conductivity type opposite the source and the same as the substrate but with greater concentration of carriers. The back contact region serves to draw stray currents but of the substrate and thereby reduce interference by substrate currents in the operation of the transistor.
In P-channel enhancement type FET's, P-regions are diffused in the surface of an N-type silicon substrate to form the spaced apart source and drain areas or regions. An N+ diffusion is used to form a back contact region adjacent to the source region. A silicon dioxide layer or oxide layer is formed over the surface with appropriate windows for leads. Metal layer strips or leads are then formed to provide the source lead, drain lead and gate. The back contact region is electrically coupled to the source. In N-channel enhancement type FET's, N regions are diffused in the surface of a P-type well formed in the silicon substrate to provide the spaced apart source and drain regions. A P+ diffusion forms the back contact region adjacent to the source. An insulating oxide layer is similarly formed over the surface with metal layer strips for the leads and gate.
In CMOS integrated circuits P-channel and N-channel transistors are coupled in complementary pairs. Typically the gates are coupled together to provide an input, the drains are coupled together to provide an output, and one source is coupled to the voltage power supply while the other is coupled to ground. An input signal turns one transistor of the CMOS pair on and the other off so that virtually no current flows except when the output switches from one state to another. Power dissipation is very low and the noise margin high.
The efficiency and switching speed of MOS and CMOS transistors are primarily a function of the channel resistance between the source and drain regions and the output or load capacitance. The channel resistance depends on the geometry of the channel and can be reduced by decreasing the length of the transistor channel, that is the distance between source and drain regions, and increasing the width or cross sectional area of the channel. The output capacitance is a function of the area size of the drain region and can be minimized by making the drain region smaller.
In order to improve the performance of FET's in MOS and CMOS integrated circuits, distributed MOS and CMOS transistor structures have been developed to reduce drain size and drain area thereby reducing output load capacitance, and to increase FET channel width relative to length to reduce channel resistance. According to the current CMOS distributed transistor structure, for example P-channel and N-channel CMOS FET's, the source element and drain element of the transistor are divided and distributed into an array of a plurality of alternating spaced apart source and drain regions distributed in a "checkerboard" of diagonal rows. Similarly, the gate element of the distributed transistor is distributed across the array in the form of two sets of orthogonally intersecting diagonal lines, strips or tracks of conductive polysilicon or other conductive material overlapping adjacent source and drain areas. As a result, a plurality of functional FET areas or regions are distributed across the array. The grid of intersecting diagonal polysilicon tracks is dielectrically isolated from the array of source and drain regions by an insulating layer of silicon dioxide referred to as the oxide layer.
For a P-Channel FET, this initial structure is formed by growing an insulating oxide layer across the N-type silicon substrate and depositing the first grid of two sets diagonal orthogonally intersecting polysilicon gate lines or tracks over the oxide layer. After preparation for the self-aligned mask procedure, P-type dopant material is diffused into the source and drain regions defined by the openings in the first grid of polysilicon gate lines. Lateral diffusion of the source and drain regions underlies the gate lines or tracks forming distributed FET areas or regions across the array.
The diffusion step also diffuses dopant molecules into the grid of polysilicon gate lines so that the gate lines are conductive. These orthogonally intersecting diagonal polysilicon gate lines or strips of the distributed gate element are electrically coupled together to provide a single gate distributed across the array. Additional masking and diffusion steps may be included in the fabrication process to distribute back contact regions of polarity or conductivity opposite the source and drain regions adjacent to the source regions.
Following growth of another oxide layer a second grid of either horizontal or vertical metal layer strips is formed over the array to provide source and drain leads dielectrically isolated from the first grid of diagonal polysilicon lines. The metal layer strip source leads contact the source regions through windows in the oxide layers while the drain leads penetrate through to the drain regions. The source leads are electrically coupled to provide a single distributed source lead across the array while the drain leads are similarly coupled.
The orthogonally intersecting diagonal polysilicon gate lines or strips of the distributed gate are electrically coupled together to provide a single distributed gate across the array.
As a result of the distribution of source regions around a single drain region, the area of the drain regions and the output capacitance of the transistor are reduced in comparison with undistributed MOS and CMOS FET structures such as single stripe and double stripe FET's. Furthermore, the width of the FET elements relative to channel length is improved thereby reducing channel resistance.